Product Information

The IDE Controller PMC, when mated to a host or carrier card, provides an interface between the PCI bus and as many as four IDE/ATA devices, via two independent channels.

Built around a Silicon Image PCI-680 IDE controller chipset, the product supports the Ultra 133 data-transfer protocol over primary and secondary IDE channels. It also supports slower bus-master data transfer rates to accommodate hard disk drives (HDDs) that do not support Ultra 133.

The primary IDE interface appears at the front-panel and also at one of the two on-board Compact Flash sockets. Two front-panel connector options are available. Depending on customer requirements, the IDE Controller PMC is manufactured with either a 40-pin, 0.100” pitch connector (P/N 5251), for the standard IDE interface, or a 44-pin, 2mm pitch connector (P/N 5252) for the Small Form Factor (SFF) connector specification.

The PCI bus operates at 33 MHz, 32 bit. Phase Locked Loops inside the 680 chip generate the necessary clocks from the PCI clock for supporting Ultra 133 transfers. Both 3.3V and 5V PCI bus signaling is supported.

The secondary IDE interface appears at the rear I/O connector (PN4) on the PMC and can be connected to the VMEbus P2 connector of a host or carrier card supporting rear I/O connectivity. One of the two Compact Flash devices is also connected to the secondary IDE interface.

The IDE controller PMC also supports two sites for mounting CompactFlash cards, one per channel. Both sites are configured to operate in true IDE mode. Additionally, each site can be set to operate in either master or slave mode.

To assure connection integrity, the CompactFlash cards can be secured to the IDE Controller PMC using a combination of locking mechanisms to prevent lateral movement and/or incidental card extraction due to shock or vibration.

DMA transfers signals to the Compact Flash sites is supported.

On-board BIOS, provided by Silicon Image and resident in flash memory, supports boot up configuration. This feature is supported only on Intel platforms.

Two LEDs are provided to monitor disk activity on the two IDE channels. The IDE Controller PMC supports four interrupts. Interrupt configuration is managed by DIP switch settings. Default setting is Interrupt A.

The 5251/5252 products are RoHS compliant follow-on products to the original 3016/3240 products. Note that these are all architecturally

similar, but the newer generation products (5251/5252) use the Silicon Image 680 chip while the older products use the Silicon Image 648 chip.

Operating System support is provided by drivers located at Silicon Image’s website (www.siimage.com).